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39 lines
886 B
Systemverilog
39 lines
886 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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interface class ICls;
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pure virtual function string get();
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endclass
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class Cls;
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string name;
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ICls icls;
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function new(string name, ICls icls);
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this.name = name;
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this.icls = icls;
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endfunction
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endclass
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class Testcase implements ICls;
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Cls cls = new("test_class", this);
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virtual function string get();
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return "In ICls";
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endfunction
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endclass
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module t(/*AUTOARG*/);
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initial begin
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Testcase test;
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test = new;
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if (test.cls.name != "test_class") $stop;
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if (test.cls.icls.get() != "In ICls") $stop;
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test.cls.icls = null; // Prevent leak
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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