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20 lines
461 B
Coq
20 lines
461 B
Coq
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Outputs
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outwires,
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// Inputs
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inwires
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);
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input [7:0] inwires [12:10];
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output wire [7:0] outwires [12:10];
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assign outwires[10] = inwires[11];
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assign outwires[11] = inwires[12];
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assign outwires[12] = inwires[13]; // must be an error here
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endmodule
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