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verilator/test_regress/t/t_debug_emitv.out

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Fix test
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module Vt_debug_emitv_t;
Cleanup and test EmitV for internal coverage
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input logic clk;
input logic in;
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typedef
???? // ENUMDTYPE 't.e_t'
???? // ENUMITEM 'ZERO'
32'h0
???? // ENUMITEM 'ONE'
'sh1
???? // REFDTYPE 'e_t'
struct packed
{
???? // REFDTYPE 'e_t'
a}signed logic [2:0] struct
{signed logic [2:0] a}logicunion
{logic a}
???? // REFDTYPE 'ps_t'
bit [31:0] const
???? // REFDTYPE 'ps_t'
const
???? // REFDTYPE 'ps_t'
[0:2]
???? // REFDTYPE 'us_t'
???? // REFDTYPE 'union_t'
signed int [31:0] signed int [31:0] [0:2]logic [15:0] logic [15:0] logic [15:0] signed int [31:0] signed int [31:0] signed int [31:0]
???? // QUEUEDTYPE
signed int [31:0] string
???? // ASSOCARRAYDTYPE
signed int [31:0]
???? // UNSIZEDARRAYDTYPE
???? // DYNARRAYDTYPE
signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed realstringIData [31:0] signed logic [31:0] signed int [31:0] logic [2:0] logic [0:0] e_t;
typedef struct packed
{
???? // REFDTYPE 'e_t'
a}signed logic [2:0] struct
{signed logic [2:0] a}logicunion
{logic a}
???? // REFDTYPE 'ps_t'
bit [31:0] const
???? // REFDTYPE 'ps_t'
const
???? // REFDTYPE 'ps_t'
[0:2]
???? // REFDTYPE 'us_t'
???? // REFDTYPE 'union_t'
signed int [31:0] signed int [31:0] [0:2]logic [15:0] logic [15:0] logic [15:0] signed int [31:0] signed int [31:0] signed int [31:0]
???? // QUEUEDTYPE
signed int [31:0] string
???? // ASSOCARRAYDTYPE
signed int [31:0]
???? // UNSIZEDARRAYDTYPE
???? // DYNARRAYDTYPE
signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed realstringIData [31:0] signed logic [31:0] signed int [31:0] logic [2:0] logic [0:0] ps_t;
typedef struct
{signed logic [2:0] a}logicunion
{logic a}
???? // REFDTYPE 'ps_t'
bit [31:0] const
???? // REFDTYPE 'ps_t'
const
???? // REFDTYPE 'ps_t'
[0:2]
???? // REFDTYPE 'us_t'
???? // REFDTYPE 'union_t'
signed int [31:0] signed int [31:0] [0:2]logic [15:0] logic [15:0] logic [15:0] signed int [31:0] signed int [31:0] signed int [31:0]
???? // QUEUEDTYPE
signed int [31:0] string
???? // ASSOCARRAYDTYPE
signed int [31:0]
???? // UNSIZEDARRAYDTYPE
???? // DYNARRAYDTYPE
signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed realstringIData [31:0] signed logic [31:0] signed int [31:0] logic [2:0] logic [0:0] us_t;
typedef union
{logic a}
???? // REFDTYPE 'ps_t'
bit [31:0] const
???? // REFDTYPE 'ps_t'
const
???? // REFDTYPE 'ps_t'
[0:2]
???? // REFDTYPE 'us_t'
???? // REFDTYPE 'union_t'
signed int [31:0] signed int [31:0] [0:2]logic [15:0] logic [15:0] logic [15:0] signed int [31:0] signed int [31:0] signed int [31:0]
???? // QUEUEDTYPE
signed int [31:0] string
???? // ASSOCARRAYDTYPE
signed int [31:0]
???? // UNSIZEDARRAYDTYPE
???? // DYNARRAYDTYPE
signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed realstringIData [31:0] signed logic [31:0] signed int [31:0] logic [2:0] logic [0:0] union_t;
struct packed
{
???? // REFDTYPE 'e_t'
a} ps[0:2];
struct
{signed logic [2:0] a} us;
union
{logic a} unu;
signed int [31:0] array[0:2];
Cleanup and test EmitV for internal coverage
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initial begin
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array = '{0:32'sh1, 1:32'sh2, 2:32'sh3};
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end
Fix test
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logic [15:0] pubflat;
logic [15:0] pubflat_r;
logic [15:0] pubflat_w;
assign pubflat_w = pubflat;
signed int [31:0] fd;
signed int [31:0] i;
Do not emit leading spaces on blank lines (#3007)
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Fix test
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???? // QUEUEDTYPE
q;
???? // ASSOCARRAYDTYPE
assoc;
???? // DYNARRAYDTYPE
dyn;
task t;
$display("stmt");
endtask
function f;
input signed int [31:0] v;
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begin : label0
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$display("stmt");
f = ((v == 'sh0) ? 'sh63 : ((~ v) + 'sh1));
disable label0;
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end
Fix test
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endfunction
initial begin
begin : unnamedblk1
signed int [31:0] other;
begin
begin : unnamedblk2
signed int [31:0] i;
i = 'sh0;
while ((i < 'sh3)) begin
begin
other = f(i);
$display("stmt %~ %~",
iother, other);
Make all expressions derive from AstNodeExpr (#3721). Apart from the representational changes below, this patch renames AstNodeMath to AstNodeExpr, and AstCMath to AstCExpr. Now every expression (i.e.: those AstNodes that represent a [possibly void] value, with value being interpreted in a very general sense) has AstNodeExpr as a super class. This necessitates the introduction of an AstStmtExpr, which represents an expression in statement position, e.g : 'foo();' would be represented as AstStmtExpr(AstCCall(foo)). In exchange we can get rid of isStatement() in AstNodeStmt, which now really always represent a statement Peak memory consumption and verilation speed are not measurably changed. Partial step towards #3420
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t();
end
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i = (i + 'h1);
end
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end
Fix test
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end
begin : named
$display("stmt");
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end
end
Fix test
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end
final begin
begin
$display("stmt");
Internal coverage improvements
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end
Cleanup and test EmitV for internal coverage
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end
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
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always @([changed] in) begin
Fix test
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begin
$display("stmt");
end
Cleanup and test EmitV for internal coverage
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end
Fix test
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always @(posedge clk) begin
begin
$display("posedge clk");
pubflat_r <= pubflat_w;
end
Cleanup and test EmitV for internal coverage
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end
always @(negedge clk) begin
Fix test
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begin
$display("negedge clk, pfr = %x", pubflat_r);
end
end
signed int [31:0] cyc;
signed int [31:0] fo;
signed int [31:0] sum;
signed real r;
string str;
always @(posedge clk) begin
begin
cyc <= (cyc + 'sh1);
r <= (r + 0.01);
fo = cyc;
Make all expressions derive from AstNodeExpr (#3721). Apart from the representational changes below, this patch renames AstNodeMath to AstNodeExpr, and AstCMath to AstCExpr. Now every expression (i.e.: those AstNodes that represent a [possibly void] value, with value being interpreted in a very general sense) has AstNodeExpr as a super class. This necessitates the introduction of an AstStmtExpr, which represents an expression in statement position, e.g : 'foo();' would be represented as AstStmtExpr(AstCCall(foo)). In exchange we can get rid of isStatement() in AstNodeStmt, which now really always represent a statement Peak memory consumption and verilation speed are not measurably changed. Partial step towards #3420
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sub.inc(fosum);
sum = sub.f(sum);
Fix test
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$display("[%0t] sum = %~", $timesum, sum);
$display("a?= %d", ($c('sh1) ? $c('sh14)
: $c('sh1e)));
$c(;);
$display("%d", $c(0));
$fopen(72'h2f6465762f6e756c6c);
$fclose(fd);
$fopen(72'h2f6465762f6e756c6c, 8'h72);
$fgetc(fd);
$fflush(fd);
$fscanf(fd, "%d", sum);
;
$fdisplay(32'h69203d20, "%~", sum);
$fwrite(fd, "hello");
$readmemh(fd, array);
$readmemh(fd, array, 'sh0);
$readmemh(fd, array, 'sh0, 'sh0);
sum = 'sh0;
begin : unnamedblk3
signed int [31:0] i;
i = 'sh0;
begin : label0
while ((i < cyc)) begin
begin
sum = (sum + i);
if ((sum > 'sha)) begin
disable label0;
end
else begin
sum = (sum + 'sh1);
end
end
i = (i + 'h1);
end
end
end
if ((cyc == 'sh63)) begin
$finish;
end
if ((cyc == 'sh64)) begin
$stop;
end
case (in)
'sh1: begin $display("1");
end
default: begin $display("default");
end
endcase
priority case (in)
'sh1: begin $display("1");
end
default: begin $display("default");
end
endcase
unique case (in)
'sh1: begin $display("1");
end
default: begin $display("default");
end
endcase
unique0 case (in)
'sh1: begin $display("1");
end
default: begin $display("default");
end
endcase
if (in) begin
$display("1");
end
else begin
$display("0");
end
priority if (in) begin
$display("1");
end
else begin
$display("0");
end
unique if (in) begin
$display("1");
end
else begin
$display("0");
end
unique0 if (in) begin
$display("1");
end
else begin
$display("0");
end
$display("%~%~", $past(cyc)$past(cyc, 'sh1),
$past(cyc, 'sh1));
str = $sformatf("cyc=%~", cyc);
;
$display("str = %@", str);
$display("%% [%t] [%^] to=%o td=%d", $time
$realtime$time$time, $realtime
$time$time, $time$time, $time);
$sscanf(40'h666f6f3d35, "foo=%d", i);
;
$printtimescale;
if ((i != 'sh5)) begin
$stop;
end
sum =
???? // RAND
;
sum =
???? // RAND
'sha;
sum =
???? // RAND
;
sum =
???? // RAND
'sha;
if ((PKG_PARAM != 'sh1)) begin
$stop;
end
sub.r = 62;
$display("%g", $log10(r));
$display("%g", $ln(r));
$display("%g", $exp(r));
$display("%g", $sqrt(r));
$display("%g", $floor(r));
$display("%g", $ceil(r));
$display("%g", $sin(r));
$display("%g", $cos(r));
$display("%g", $tan(r));
$display("%g", $asin(r));
$display("%g", $acos(r));
$display("%g", $atan(r));
$display("%g", $sinh(r));
$display("%g", $cosh(r));
$display("%g", $tanh(r));
$display("%g", $asinh(r));
$display("%g", $acosh(r));
$display("%g", $atanh(r));
Tests: Fix some force/release coverage holes.
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force sum = 'sha;
__Vrepeat0 = 'sh2;
while ((__Vrepeat0 > 32'h0)) begin
if ((sum != 'sha)) begin
$stop;
end
__Vrepeat0 = (__Vrepeat0 - 32'h1);
end
release sum;
Fix test
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end
Cleanup and test EmitV for internal coverage
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end
Fix test
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/*verilator public_flat_rw @(posedge clk) pubflat*/
Tests: Fix some force/release coverage holes.
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signed integer [31:0] __Vrepeat0;
Cleanup and test EmitV for internal coverage
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endmodule
Misc internal coverage cleanups
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package Vt_debug_emitv___024unit;
Fix test
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class Vt_debug_emitv_Cls;
signed int [31:0] member;
member = 'sh1;
task method;
endtask
task new;
endtask
endclass
Misc internal coverage cleanups
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endpackage
Fix test
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module Vt_debug_emitv_sub;
task inc;
input signed int [31:0] i;
output signed int [31:0] o;
o = ({32'h1{{1'h0, i[31:1]}}} + 32'h1);
endtask
function f;
input signed int [31:0] v;
begin : label0
begin : label0
if ((v == 'sh0)) begin
f = 'sh21;
disable label0;
end
f = ({32'h1{{31'h0, v[2]}}} + 32'h1);
disable label0;
end
end
endfunction
signed real r;
endmodule
Misc internal coverage cleanups
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package Vt_debug_emitv_Pkg;
Fix test
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signed logic [31:0] PKG_PARAM;
Misc internal coverage cleanups
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endpackage
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