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31 lines
596 B
Coq
31 lines
596 B
Coq
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2010 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Outputs
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hval,
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// Inputs
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sel
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);
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input logic [2:0] sel;
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output logic [3:0] hval;
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/*AUTOINPUT*/
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/*AUTOOUTPUT*/
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always_comb begin
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unique case (sel)
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3'h0: hval = 4'hd;
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3'h1: hval = 4'hc;
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3'h7: hval = 4'hf;
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default: begin
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$ignore ("ERROR : %s [%m]", $sformatf ("Illegal sel = %x", sel));
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hval = 4'bx;
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end
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endcase
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end
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endmodule
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