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22 lines
525 B
Systemverilog
22 lines
525 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define STRINGIFY(x) `"x`"
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module t #(
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parameter int POVERRODE = 16,
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parameter int PORIG = 16
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) (/*AUTOARG*/);
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initial begin
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$dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"});
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$dumpvars;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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