mirror of
https://github.com/verilator/verilator.git
synced 2025-01-23 23:04:14 +00:00
13 lines
296 B
Systemverilog
13 lines
296 B
Systemverilog
|
// DESCRIPTION: Verilator: Verilog Test module
|
||
|
|
//
|
||
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||
|
|
// any use, without warranty, 2020 Rafal Kapuscik
|
||
|
|
// SPDX-License-Identifier: CC0-1.0
|
||
|
|
//
|
||
|
|
|
||
|
|
class Cls;
|
||
|
|
task t;
|
||
|
|
super.i = 1; // Bad - no extends
|
||
|
|
endtask
|
||
|
|
endclass
|