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34 lines
941 B
Coq
34 lines
941 B
Coq
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t (/*AUTOARG*/);
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integer a, b;
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initial begin
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for (; ; ) ;
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for (; ; a=a+1) ;
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for (; ; a=a+1, b=b+1) ;
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for (; a<1; ) ;
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for (; a<1; a=a+1) ;
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for (; a<1; a=a+1, b=b+1) ;
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for (a=0; a<1; ) ;
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for (a=0; a<1; a=a+1) ;
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for (a=0; a<1; a=a+1, b=b+1) ;
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for (integer a=0; a<1; ) ;
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for (integer a=0; a<1; a=a+1) ;
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for (integer a=0; a<1; a=a+1, b=b+1) ;
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for (var integer a=0; a<1; ) ;
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for (var integer a=0; a<1; a=a+1) ;
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for (var integer a=0; a<1; a=a+1, b=b+1) ;
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for (integer a=0, integer b=0; a<1; ) ;
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for (integer a=0, integer b=0; a<1; a=a+1) ;
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for (integer a=0, integer b=0; a<1; a=a+1, b=b+1) ;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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