mirror of
https://github.com/verilator/verilator.git
synced 2025-01-10 08:37:35 +00:00
13 lines
238 B
Coq
13 lines
238 B
Coq
|
// DESCRIPTION: Verilator: Verilog Test module
|
||
|
|
//
|
||
|
|
// This file ONLY is placed into the Public Domain, for any use,
|
||
|
|
// without warranty, 2010 by Wilson Snyder.
|
||
|
|
|
||
|
|
module t
|
||
|
|
(
|
||
|
|
input wire i,
|
||
|
|
input wire i2 = i // BAD
|
||
|
|
);
|
||
|
|
|
||
|
|
endmodule
|