mirror of
https://github.com/verilator/verilator.git
synced 2025-01-13 18:14:17 +00:00
4 lines
47 B
Systemverilog
4 lines
47 B
Systemverilog
|
module a;
|
||
|
|
initial $lay(*Hello!=n");
|
||
|
|
endmodule
|