verilator/test_regress/t/t_flag_errorlimit_bad.v

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0

module t (/*AUTOARG*/);

   int u1;
   int u1;
   int u1;
   int u1;
   int u1;
   int u1;
   int u1;

endmodule
Tests: Cover --error-limit and update docs (found via coverage). 2019-07-01 01:36:57 +00:00			`// DESCRIPTION: Verilator: Verilog Test module`
			`//`
Add SPDX license identifiers. No functional change. 2020-03-21 15:24:24 +00:00			`// This file ONLY is placed under the Creative Commons Public Domain, for`
			`// any use, without warranty, 2019 by Wilson Snyder.`
			`// SPDX-License-Identifier: CC0-1.0`
Tests: Cover --error-limit and update docs (found via coverage). 2019-07-01 01:36:57 +00:00
			`module t (/AUTOARG/);`

			`int u1;`
			`int u1;`
			`int u1;`
			`int u1;`
			`int u1;`
			`int u1;`
			`int u1;`

			`endmodule`