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31 lines
833 B
Systemverilog
31 lines
833 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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typedef class Cls;
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class Cls;
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int imembera;
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function int get_methoda; return imembera; endfunction
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task set_methoda(input int val); imembera = val; endtask
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function void setv_methoda(input int val); imembera = val; endfunction
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endclass : Cls
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module t (/*AUTOARG*/);
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initial begin
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Cls c;
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if (c != null) $stop;
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c = new;
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c.imembera = 10;
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if (c.get_methoda() != 10) $stop;
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c.set_methoda(20);
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if (c.get_methoda() != 20) $stop;
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c.setv_methoda(30);
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if (c.get_methoda() != 30) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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