mirror of
https://github.com/verilator/verilator.git
synced 2025-01-10 08:37:35 +00:00
23 lines
867 B
Perl
23 lines
867 B
Perl
|
#!/usr/bin/perl
|
||
|
|
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||
|
|
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||
|
|
#
|
||
|
|
# Copyright 2008 by Wilson Snyder. This program is free software; you can
|
||
|
|
# redistribute it and/or modify it under the terms of either the GNU
|
||
|
|
# Lesser General Public License Version 3 or the Perl Artistic License
|
||
|
|
# Version 2.0.
|
||
|
|
|
||
|
|
compile (
|
||
|
|
v_flags2 => ["--lint-only"],
|
||
|
|
fails=>1,
|
||
|
|
expect=>
|
||
|
|
'%Warning-IMPLICIT: t/t_lint_implicit_def_bad.v:\d+: Signal definition not found, creating implicitly: imp_warn
|
||
|
|
%Warning-IMPLICIT: Use "/\* verilator lint_off IMPLICIT \*/" and lint_on around source to disable this message.
|
||
|
|
%Error: t/t_lint_implicit_def_bad.v:\d+: Signal definition not found, and implicit disabled with `default_nettype: imp_err
|
||
|
|
%Error: Exiting due to.*',
|
||
|
|
) if $Self->{v3};
|
||
|
|
|
||
|
|
ok(1);
|
||
|
|
1;
|
||
|
|
|