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47 lines
1.2 KiB
Coq
47 lines
1.2 KiB
Coq
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2010 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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import "DPI-C" context function integer mon_check();
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg onebit /*verilator public_flat_rw @(posedge clk) */;
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reg [2:1] twoone /*verilator public_flat_rw @(posedge clk) */;
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reg [4:3][2:1] fourthreetwoone /*verilator public_flat_rw @(posedge clk) */;
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reg [3:2][61:0] quads /*verilator public_flat_rw @(posedge clk) */;
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integer status;
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sub sub();
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// Test loop
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initial begin
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onebit = 1'b0;
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status = mon_check();
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if (status!=0) begin
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$write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status);
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$stop;
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end
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if (onebit != 1'b1) $stop;
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if (quads[2] != 62'h12819213_abd31a1c) $stop;
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if (quads[3] != 62'h1c77bb9b_3784ea09) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module sub;
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reg subsig1 /*verilator public_flat_rd*/;
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reg subsig2 /*verilator public_flat_rd*/;
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endmodule
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