mirror of
https://github.com/verilator/verilator.git
synced 2025-01-08 15:47:36 +00:00
6 lines
257 B
Plaintext
6 lines
257 B
Plaintext
|
%Error: t/t_clocking_bad1.v:16:12: Only one default clocking block allowed per module (IEEE 1800-2017 14.12)
|
||
|
|
: ... In instance t
|
||
|
|
16 | default clocking @(posedge clk);
|
||
|
|
| ^~~~~~~~
|
||
|
|
%Error: Exiting due to
|