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14 lines
235 B
Systemverilog
14 lines
235 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2018 by Wilson Snyder.
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package defs;
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int sig;
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endpackage
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import defs::*;
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module t;
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endmodule
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