2006-08-26 11:35:28 +00:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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2020-03-21 15:24:24 +00:00
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2004 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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2006-08-26 11:35:28 +00:00
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module t;
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2019-07-14 00:30:32 +00:00
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`define DEFINED
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2006-08-26 11:35:28 +00:00
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2019-07-14 00:30:32 +00:00
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// NDEFINED isn't defined here:
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`NDEFINED
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2006-08-26 11:35:28 +00:00
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2019-07-14 00:30:32 +00:00
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// Botched directive (`timescale)
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`imescale
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2006-08-26 11:35:28 +00:00
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initial $stop; // Should have failed
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endmodule
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