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https://github.com/verilator/verilator.git
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58 lines
707 B
Plaintext
58 lines
707 B
Plaintext
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$date
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Tue Aug 28 17:08:13 2018
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$end
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$version
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lxt2vcd
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$end
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$timescale 1ns $end
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$scope module top $end
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$var wire 1 ! clk $end
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$scope module t $end
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$scope module biggie $end
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$var wire 1048577 " d [1048576:0] $end
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$upscope $end
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$var wire 32 # cyc [31:0] $end
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$var wire 1 ! clk $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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$dumpvars
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#0
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0!
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b0 "
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b0 #
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#10
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b1 #
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b111111101110110111111010110011100 "
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1!
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#15
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0!
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#20
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1!
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b1111111011101101111110101100111000 "
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b10 #
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#25
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0!
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#30
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1!
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b11 #
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b11111110111011011111101011001110000 "
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#35
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0!
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#40
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1!
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b111111101110110111111010110011100000 "
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b100 #
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#45
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0!
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#50
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1!
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b101 #
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b1111111011101101111110101100111000000 "
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#55
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0!
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#60
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1!
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b11111110111011011111101011001110000000 "
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b110 #
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