mirror of
https://github.com/verilator/verilator.git
synced 2025-01-10 08:37:35 +00:00
10 lines
265 B
Systemverilog
10 lines
265 B
Systemverilog
|
// DESCRIPTION: Verilator: Large test for SystemVerilog
|
||
|
|
|
||
|
|
// This file ONLY is placed into the Public Domain, for any use,
|
||
|
|
// without warranty, 2012.
|
||
|
|
|
||
|
|
// Contributed by M W Lund, Atmel Corporation.
|
||
|
|
|
||
|
|
// **** Set simulation time scale ****
|
||
|
|
`timescale 1ns/1ps
|