verilator/test_regress/t/t_trace_complex_structs.out

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$version Generated by VerilatedVcd $end
$date Sat Mar 8 15:28:22 2014
$end
$timescale 1ns $end
$scope module top $end
$var wire 1 ; clk $end
$scope module v $end
$var wire 1 ; clk $end
$var wire 32 # cyc [31:0] $end
$var wire 2 , v_arrp [2:1] $end
$var wire 2 - v_arrp_arrp(3) [1:0] $end
$var wire 2 . v_arrp_arrp(4) [1:0] $end
$var wire 1 < v_arru(1) $end
$var wire 1 = v_arru(2) $end
$var wire 2 3 v_arru_arrp(3) [2:1] $end
$var wire 2 4 v_arru_arrp(4) [2:1] $end
$var wire 1 > v_arru_arru(3)(1) $end
$var wire 1 ? v_arru_arru(3)(2) $end
$var wire 1 @ v_arru_arru(4)(1) $end
$var wire 1 A v_arru_arru(4)(2) $end
$scope module p2 $end
$var wire 32 B P [31:0] $end
$upscope $end
$scope module p3 $end
$var wire 32 C P [31:0] $end
$upscope $end
$scope module unnamedblk1 $end
$var wire 32 9 b [31:0] $end
$scope module unnamedblk2 $end
$var wire 32 : a [31:0] $end
$upscope $end
$upscope $end
$scope module v_arrp_strp(3) $end
$var wire 1 0 b0 $end
$var wire 1 / b1 $end
$upscope $end
$scope module v_arrp_strp(4) $end
$var wire 1 2 b0 $end
$var wire 1 1 b1 $end
$upscope $end
$scope module v_arru_strp(3) $end
$var wire 1 6 b0 $end
$var wire 1 5 b1 $end
$upscope $end
$scope module v_arru_strp(4) $end
$var wire 1 8 b0 $end
$var wire 1 7 b1 $end
$upscope $end
$scope module v_strp $end
$var wire 1 % b0 $end
$var wire 1 $ b1 $end
$upscope $end
$scope module v_strp_strp $end
$scope module x0 $end
$var wire 1 ) b0 $end
$var wire 1 ( b1 $end
$upscope $end
$scope module x1 $end
$var wire 1 ' b0 $end
$var wire 1 & b1 $end
$upscope $end
$upscope $end
$scope module v_unip_strp $end
$scope module x0 $end
$var wire 1 + b0 $end
$var wire 1 * b1 $end
$upscope $end
$scope module x1 $end
$var wire 1 + b0 $end
$var wire 1 * b1 $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
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