verilator/test_regress/t/t_select_bad_msb.out

%Warning-LITENDIAN: t/t_select_bad_msb.v:11: Little bit endian vector: MSB < LSB of bit range: 0:22
   reg [0:22] backwd;
       ^
                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.
%Error: t/t_select_bad_msb.v:15: [1:4] Range extract has backward bit ordering, perhaps you wanted [4:1]
                               : ... In instance t
      sel2 = mi[1:4];
               ^
%Error: Exiting due to
Tests: Add additional .out files instead of expects. 2019-06-13 01:49:40 +00:00			`%Warning-LITENDIAN: t/t_select_bad_msb.v:11: Little bit endian vector: MSB < LSB of bit range: 0:22`
When showing an error, show source code. 2019-07-15 01:42:03 +00:00			`reg [0:22] backwd;`
			`^`
Tests: Add additional .out files instead of expects. 2019-06-13 01:49:40 +00:00			`... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.`
			`%Error: t/t_select_bad_msb.v:15: [1:4] Range extract has backward bit ordering, perhaps you wanted [4:1]`
When showing an error, show the instance location 2019-07-26 16:52:38 +00:00			`: ... In instance t`
When showing an error, show source code. 2019-07-15 01:42:03 +00:00			`sel2 = mi[1:4];`
			`^`
Tests: Add additional .out files instead of expects. 2019-06-13 01:49:40 +00:00			`%Error: Exiting due to`