2006-08-26 11:35:28 +00:00
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#!/usr/bin/perl
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2008-09-23 14:02:31 +00:00
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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2006-08-26 11:35:28 +00:00
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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2008-09-23 14:02:31 +00:00
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# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
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2006-08-26 11:35:28 +00:00
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# redistribute it and/or modify it under the terms of either the GNU
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# General Public License or the Perl Artistic License.
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top_filename("t/t_assert_synth.v");
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compile (
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v_flags2 => [$Last_Self->{v3}?'--assert':($Last_Self->{nc}?'+assert':''),
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'+define+FAILING_PARALLEL',],
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);
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execute (
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check_finished=>0,
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fails=>1,
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expect=>
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'%Error: t_assert_synth.v:\d+: Assertion failed in TOP.v: synthesis parallel_case'
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);
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ok(1);
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1;
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