verilator/test_regress/t/t_lint_pinmissing_bad.v

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2012 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0

module t;
   sub sub();  // <--- Warning
endmodule
module sub
  (output port);
endmodule