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32 lines
594 B
Systemverilog
32 lines
594 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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process p;
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bit s = 0;
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initial begin
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wait (s);
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p.kill();
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p.await();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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always @(posedge clk) begin
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if (!p) begin
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p = process::self();
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s = 1;
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end else begin
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$stop;
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end
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end
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endmodule
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