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60 lines
1.5 KiB
Systemverilog
60 lines
1.5 KiB
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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interface Iface;
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logic clk = 1'b0, inp = 1'b0, io = 1'b0, out = 1'b0, out2 = 1'b0;
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clocking cb @(posedge clk);
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input #7 inp;
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output out;
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inout io;
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endclocking
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always @(posedge clk) inp <= 1'b1;
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always #5 clk <= ~clk;
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assign out2 = out;
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endinterface
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module main;
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initial begin
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#6;
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t.mod1.cb.io <= 1'b1;
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t.mod1.cb.out <= 1'b1;
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if (t.mod0.io != 1'b0) $stop;
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if (t.mod1.cb.io != 1'b0) $stop;
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if (t.mod1.cb.inp != 1'b0) $stop;
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@(posedge t.mod0.io)
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if ($time != 15) $stop;
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if (t.mod0.io != 1'b1) $stop;
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if (t.mod1.cb.io != 1'b0) $stop;
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#1
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if (t.mod0.cb.io != 1'b1) $stop;
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if (t.mod1.cb.io != 1'b1) $stop;
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if (t.mod1.cb.inp != 1'b1) $stop;
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#8;
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t.mod0.inp = 1'b0;
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if (t.mod0.cb.inp != 1'b1) $stop;
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@(t.mod1.cb)
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if ($time != 25) $stop;
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if (t.mod0.cb.inp != 1'b1) $stop;
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t.mod0.inp = 1'b0;
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@(t.mod0.cb)
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if ($time != 35) $stop;
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if (t.mod0.cb.inp != 1'b0) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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initial begin
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@(posedge t.mod0.out)
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if ($time != 15) $stop;
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if (t.mod1.out2 != 1'b1) $stop;
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end
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endmodule
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module t;
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main main1();
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Iface mod0();
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virtual Iface mod1 = mod0;
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endmodule
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