mirror of
https://github.com/verilator/verilator.git
synced 2025-01-09 16:17:36 +00:00
20 lines
474 B
Coq
20 lines
474 B
Coq
|
// DESCRIPTION: Verilator: Verilog Test module
|
||
|
//
|
||
|
// This file ONLY is placed into the Public Domain, for any use,
|
||
|
// without warranty, 2009 by Wilson Snyder.
|
||
|
|
||
|
module t;
|
||
|
|
||
|
`define UDALL
|
||
|
`ifndef PREDEF_COMMAND_LINE `error "Test setup error, PREDEF_COMMAND_LINE pre-missing" `endif
|
||
|
|
||
|
`undefineall
|
||
|
|
||
|
`ifdef UDALL `error "undefineall failed" `endif
|
||
|
`ifndef PREDEF_COMMAND_LINE `error "Deleted too much, no PREDEF_COMMAND_LINE" `endif
|
||
|
|
||
|
initial begin
|
||
|
$finish;
|
||
|
end
|
||
|
endmodule
|