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58 lines
1.7 KiB
Systemverilog
58 lines
1.7 KiB
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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typedef struct packed {
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longint a;
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longint b;
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longint c;
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} s_t;
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module t;
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localparam int c0 [4] = '{5, 6, 7, 8};
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localparam bit [255:0] c1 [4] = '{9, 10, 11, 12};
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localparam string c2 [2] = '{"baz", "quux"};
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localparam s_t c3 [2] = '{'{a: 100, b: 200, c: 300},
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'{a: 1000, b: 2000, c: 3000}};
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a #(
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.p0(c0),
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.p1(c1),
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.p2(c2),
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.p3(c3)
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) i_a ();
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endmodule
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module a
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#(
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parameter int p0 [4] = '{1, 2, 3, 4},
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parameter bit [255:0] p1 [4] = '{1, 2, 3, 4},
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parameter string p2 [2] = '{"foo", "bar"},
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parameter s_t p3 [2] = '{'{a: 1, b: 2, c: 3},
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'{a: 1, b: 2, c: 3}}
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);
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initial begin
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// Go via $c to ensure parameters are emitted
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if (p0[$c("0")] != 5) $stop;
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if (p0[$c("1")] != 6) $stop;
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if (p0[$c("2")] != 7) $stop;
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if (p0[$c("3")] != 8) $stop;
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if (p1[$c("0")] != 9) $stop;
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if (p1[$c("1")] != 10) $stop;
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if (p1[$c("2")] != 11) $stop;
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if (p1[$c("3")] != 12) $stop;
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if (p2[$c("0")] != "baz") $stop;
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if (p2[$c("1")] != "quux") $stop;
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if (p3[$c("0")].a != 100) $stop;
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if (p3[$c("0")].b != 200) $stop;
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if (p3[$c("0")].c != 300) $stop;
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if (p3[$c("1")].a != 1000) $stop;
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if (p3[$c("1")].b != 2000) $stop;
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if (p3[$c("1")].c != 3000) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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