verilator/test_regress/t/t_trace_two_dumpfst_cc.out

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$date
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Sat Mar 7 18:39:05 2020
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$end
$version
fstWriter
$end
$timescale
1ns
$end
$scope module topa $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc $end
$var integer 32 # c_trace_on $end
$scope module sub $end
$var integer 32 $ inside_sub_a $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
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1!
b00000000000000000000000000000001 "
b00000000000000000000000000000000 #
b00000000000000000000000000000001 $
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b00000000000000000000000000000011 #
b00000000000000000000000000000010 "
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b00000000000000000000000000000011 "
b00000000000000000000000000000100 #
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b00000000000000000000000000000101 #
b00000000000000000000000000000100 "
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b00000000000000000000000000000101 "
b00000000000000000000000000000110 #
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b00000000000000000000000000000111 #
b00000000000000000000000000000110 "
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b00000000000000000000000000000111 "
b00000000000000000000000000001000 #
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b00000000000000000000000000001000 "
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b00000000000000000000000000001010 #
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b00000000000000000000000000001011 #
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b00000000000000000000000000001011 "
b00000000000000000000000000001100 #