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14 lines
891 B
Plaintext
14 lines
891 B
Plaintext
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%Warning-COMBDLY: t/t_lint_latch_5.v:13:13: Non-blocking assignment '<=' in combinational logic process
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: ... This will be executed as a blocking assignment '='!
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13 | z[0] <= a[0];
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| ^~
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... For warning description see https://verilator.org/warn/COMBDLY?v=latest
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... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message.
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*** See https://verilator.org/warn/COMBDLY before disabling this,
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else you may end up with different sim results.
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%Warning-COMBDLY: t/t_lint_latch_5.v:17:13: Non-blocking assignment '<=' in combinational logic process
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: ... This will be executed as a blocking assignment '='!
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17 | z[1] <= a[1];
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| ^~
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%Error: Exiting due to
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