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29 lines
510 B
Systemverilog
29 lines
510 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2021 by Adrien Le Masle.
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// SPDX-License-Identifier: CC0-1.0
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package pack_a;
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parameter PARAM_A = 0;
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endpackage : pack_a
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//module t;
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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parameter PARAM_A = 0;
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initial begin
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$display(PARAM_A);
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if (PARAM_A != 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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