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23 lines
437 B
Systemverilog
23 lines
437 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/);
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logic never;
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initial begin
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fork
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#10;
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#10;
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join_none
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disable fork;
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wait fork;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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