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15 lines
320 B
Systemverilog
15 lines
320 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Yutetsu TAKATSUKASA
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module t;
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t_flag_relinc_sub i_t_flag_relinc_sub();
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endmodule
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`ifdef VERILATOR
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`verilator_config
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hier_block -module "t_flag_relinc_sub"
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`verilog
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`endif
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