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54 lines
1.6 KiB
Perl
54 lines
1.6 KiB
Perl
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2019 by Todd Strader. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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scenarios(
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vlt => 1,
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xsim => 1,
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);
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# Always compile the secret file with Verilator no matter what simulator
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# we are testing with
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my $cmd = ["t/t_prot_lib_secret.pl", "--vlt"];
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my $secret_prefix = "t_prot_lib_secret";
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my $secret_dir = "$Self->{obj_dir}/../../obj_vlt/$secret_prefix";
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while (1) {
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run(logfile => "$Self->{obj_dir}/secret_compile.log",
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cmd => $cmd);
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last if $Self->{errors};
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compile(
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verilator_flags2 => ["$secret_dir/secret.sv",
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"--trace", "-LDFLAGS",
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"'-L../$secret_prefix -lsecret -static'"],
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xsim_flags2 => ["$secret_dir/secret.sv"],
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);
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execute(
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check_finished => 1,
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xsim_run_flags2 => ["--debug",
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"all",
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"--sv_lib",
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"$secret_dir/libsecret",
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"--dpi_absolute"],
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);
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if ($Self->{vlt}) {
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# We can see the ports of the secret module
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file_grep("$Self->{obj_dir}/simx.vcd", qr/accum_in/);
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# but we can't see what's inside
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file_grep_not("$Self->{obj_dir}/simx.vcd", qr/secret_/);
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}
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ok(1);
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last;
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}
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1;
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