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16 lines
284 B
Systemverilog
16 lines
284 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Wilson Snyder.
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module t;
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reg foobar;
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task boobar; endtask
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initial begin
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if (foobat) $stop;
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boobat;
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end
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endmodule
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