verilator/test_regress/t/t_trace_two_a.v

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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Wilson Snyder.
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`define CONCAT(a, b) a``b
`define STRINGIFY(x) `"x`"
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module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
integer c_trace_on;
sub sub ();
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// verilator tracing_off
string filename;
// verilator tracing_on
initial begin
`ifdef TEST_FST
filename = {`STRINGIFY(`TEST_OBJ_DIR), "/simx.fst"};
`else
filename = {`STRINGIFY(`TEST_OBJ_DIR), "/simx.vcd"};
`endif
`ifdef TEST_DUMP
$dumpfile(filename);
$dumpvars(0, top);
$dumplimit(10 * 1024 * 1024);
`elsif TEST_DUMPPORTS
$dumpports(top, filename);
$dumpportslimit(10 * 1024 * 1024, filename);
`endif
end
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always @ (posedge clk) begin
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if (cyc != 0) begin
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cyc <= cyc + 1;
c_trace_on <= cyc + 2;
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if (cyc == 3) begin
`ifdef TEST_DUMP
$dumpoff;
`elsif TEST_DUMPPORTS
$dumpportsoff(filename);
`endif
end
else if (cyc == 5) begin
`ifdef TEST_DUMP
$dumpall;
$dumpflush;
`elsif TEST_DUMPPORTS
$dumpportsall(filename);
$dumpportsflush(filename);
`endif
end
else if (cyc == 7) begin
`ifdef TEST_DUMP
$dumpon;
`elsif TEST_DUMPPORTS
$dumpportson(filename);
`endif
end
else if (cyc == 10) begin
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$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module sub;
integer inside_sub_a = 1;
endmodule