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13 lines
249 B
Systemverilog
13 lines
249 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Wilson Snyder.
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//bug1587
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module t;
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reg a[0];
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reg b;
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reg c;
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initial c = (a != &b);
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endmodule
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