verilator/test_regress/t/t_sys_readmem_b_8.mem

// $Id$
// DESCRIPTION: Verilator: Verilog Test data file
//
// Copyright 2006 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// General Public License or the Perl Artistic License.

// ** Note this file has DOS CR's so we can test them!

10000
10001
10010
10011
/*
multi line
ignored
*/
10100
10101
10110
10111
Fix * with filenames < 8 characters git-svn-id: file://localhost/svn/verilator/trunk/verilator@859 77ca24e4-aefa-0310-84f0-b9a241c72d87 2006-12-21 15:28:32 +00:00			`// $Id$`
			`// DESCRIPTION: Verilator: Verilog Test data file`
			`//`
			`// Copyright 2006 by Wilson Snyder. This program is free software; you can`
			`// redistribute it and/or modify it under the terms of either the GNU`
			`// General Public License or the Perl Artistic License.`

			`// ** Note this file has DOS CR's so we can test them!`

			`10000`
			`10001`
			`10010`
			`10011`
			`/*`
			`multi line`
			`ignored`
			`*/`
			`10100`
			`10101`
			`10110`
			`10111`