verilator/test_regress/t/t_inst_misarray_bad.out

%Error: t/t_inst_misarray_bad.v:17:23: Illegal input port connection 'foo', mismatch between port which is an array, and expression which is not an array. (IEEE 1800-2017 7.6)
                                     : ... In instance t
   17 |                      .foo(foo));   
      |                       ^~~
%Error: Exiting due to