verilator/docs/gen/ex_MULTIDRIVEN_msg.rst

.. comment: generated by t_lint_multidriven_bad
.. code-block::

   %Warning-MULTIDRIVEN: example.v:1:22 Signal has multiple driving blocks with different clocking: 't.mem'
                         example.v:1:7 ... Location of first driving block
                         example.v:1:7 ... Location of other driving block
Commentary on MULTIDRIVEN (#2972). 2021-05-19 12:14:14 +00:00			`.. comment: generated by t_lint_multidriven_bad`
			`.. code-block::`

Defer conversion of set flag based AssignDlys (#5091) No functional change. Postpone the conversion of all AstAssignDlys that use the 'VdlySet' scheme for array LHSs until after the complete traversal of the netlist. The next patch takes advantage of this by using some extra information also gathered through the traversal to change the conversion. AstAssignDlys inside suspendable or fork are not deferred and are processed identical to the previous version. There are some TODOs in this patch that are fixed in the next patch. Output code perturbed due to variable ordering. MULTIDRIVEN message ordering perturbed due to processing order change. 2024-05-01 23:24:00 +00:00			`%Warning-MULTIDRIVEN: example.v:1:22 Signal has multiple driving blocks with different clocking: 't.mem'`
Commentary on MULTIDRIVEN (#2972). 2021-05-19 12:14:14 +00:00			`example.v:1:7 ... Location of first driving block`
			`example.v:1:7 ... Location of other driving block`