verilator/test_regress/t/t_var_port2_bad.v

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0

module t (portwithoin);
   input portwithin;
endmodule
Tests: Fill in some missing error coverage holes. 2019-07-12 00:18:36 +00:00			`// DESCRIPTION: Verilator: Verilog Test module`
			`//`
Add SPDX license identifiers. No functional change. 2020-03-21 15:24:24 +00:00			`// This file ONLY is placed under the Creative Commons Public Domain, for`
			`// any use, without warranty, 2019 by Wilson Snyder.`
			`// SPDX-License-Identifier: CC0-1.0`
Tests: Fill in some missing error coverage holes. 2019-07-12 00:18:36 +00:00
			`module t (portwithoin);`
			`input portwithin;`
			`endmodule`