verilator/test_regress/t/t_program.v

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2009-11-06 00:09:45 +00:00
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
2009-11-06 00:09:45 +00:00
program t;
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endprogram