mirror of
https://github.com/verilator/verilator.git
synced 2025-01-09 16:17:36 +00:00
23 lines
440 B
Coq
23 lines
440 B
Coq
|
// $Id:$
|
||
|
|
// DESCRIPTION: Verilator: Verilog Test module
|
||
|
|
//
|
||
|
|
// This file ONLY is placed into the Public Domain, for any use,
|
||
|
|
// without warranty, 2005 by Wilson Snyder.
|
||
|
|
|
||
|
|
module t (/*AUTOARG*/
|
||
|
|
// Inputs
|
||
|
|
value
|
||
|
|
);
|
||
|
|
input [3:0] value;
|
||
|
|
assign value = 4'h0;
|
||
|
|
sub sub (.valueSub (value[3:0]));
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
module sub (/*AUTOARG*/
|
||
|
|
// Inputs
|
||
|
|
valueSub
|
||
|
|
);
|
||
|
|
input [3:0] valueSub;
|
||
|
|
assign valueSub = 4'h0;
|
||
|
|
endmodule
|