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61 lines
1.2 KiB
Coq
61 lines
1.2 KiB
Coq
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// $Id:$
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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supply0 [1:0] low;
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supply1 [1:0] high;
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reg [7:0] isizedwire;
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reg ionewire;
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`ifdef never_just_for_verilog_mode
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wire oonewire; // From sub of t_inst_v2k_sub.v
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`endif
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wire [7:0] osizedreg; // From sub of t_inst_v2k_sub.v
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t_inst_v2k_sub sub
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(
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// Outputs
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.osizedreg (osizedreg[7:0]),
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// verilator lint_off IMPLICIT
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.oonewire (oonewire),
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// verilator lint_on IMPLICIT
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// Inputs
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.isizedwire (isizedwire[7:0]),
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.ionewire (ionewire));
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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if (cyc==1) begin
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ionewire <= 1'b1;
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isizedwire <= 8'd8;
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end
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if (cyc==2) begin
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if (low != 2'b00) $stop;
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if (high != 2'b11) $stop;
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if (oonewire !== 1'b1) $stop;
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if (isizedwire !== 8'd8) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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// Local Variables:
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// compile-command: "./vlint __FILE__"
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// End:
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