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45 lines
1.6 KiB
Python
45 lines
1.6 KiB
Python
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.top_filename = "t/t_dpi_var.v"
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out_filename = test.obj_dir + "/V" + test.name + ".tree.json"
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test.compile(make_top_shell=False,
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make_main=False,
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verilator_flags2=[
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"--no-json-edit-nums", "--exe --no-l2name", test.t_dir + "/t_dpi_var.vlt",
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test.t_dir + "/t_dpi_var.cpp"
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])
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if test.vlt_all:
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test.file_grep(
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out_filename,
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r'{"type":"VAR","name":"formatted","addr":"[^"]*","loc":"f,58:[^"]*",.*"origName":"formatted",.*"direction":"INPUT",.*"dtypeName":"string",.*"attrSFormat":true'
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)
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test.file_grep(
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out_filename,
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r'{"type":"VAR","name":"t.sub.in","addr":"[^"]*","loc":"f,81:[^"]*",.*"origName":"in",.*"dtypeName":"int",.*"isSigUserRdPublic":true'
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)
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test.file_grep(
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out_filename,
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r'{"type":"VAR","name":"t.sub.fr_a","addr":"[^"]*","loc":"f,82:[^"]*",.*"origName":"fr_a",.*"dtypeName":"int",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true'
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)
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test.file_grep(
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out_filename,
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r'{"type":"VAR","name":"t.sub.fr_b","addr":"[^"]*","loc":"f,83:[^"]*",.*"origName":"fr_b",.*"dtypeName":"int",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true'
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)
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test.execute()
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test.passes()
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