verilator/test_regress/t/t_wire_beh_bad.out

%Error-CONTASSREG: t/t_wire_beh_bad.v:11: Continuous assignment to reg, perhaps intended wire (IEEE 2005 6.1; Verilog only, legal in SV): r
%Error-PROCASSWIRE: t/t_wire_beh_bad.v:12: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): w
%Error: Exiting due to
Add CONTASSREG error on continuous assignments to regs, bug1369. 2018-12-01 15:12:10 +00:00			`%Error-CONTASSREG: t/t_wire_beh_bad.v:11: Continuous assignment to reg, perhaps intended wire (IEEE 2005 6.1; Verilog only, legal in SV): r`
			`%Error-PROCASSWIRE: t/t_wire_beh_bad.v:12: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): w`
Add PROCASSWIRE error on behavioral assignments to wires, msg2737. 2018-11-26 22:58:18 +00:00			`%Error: Exiting due to`