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21 lines
582 B
Systemverilog
21 lines
582 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module for Issue#1609
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Julien Margetts.
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module t (/*AUTOARG*/ i, o);
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input [1:0] i;
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output reg [1:0] o;
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// This should not detect a latch as all options are covered
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always @* begin
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if (i==2'b00) o = 2'b11;
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else if (i==2'b01) o = 2'b10;
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else if (i==2'b10) o = 2'b01;
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else if (i==2'b11) o = 2'b00;
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else o = 2'b00; // Without this else a latch is (falsely) detected
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end
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endmodule
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