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29 lines
630 B
Systemverilog
29 lines
630 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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function void test;
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automatic string s;
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s = get_randstate();
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// Vlt only result check
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if (s[0] !== "R") $fatal(2, $sformatf("Bad get_randstate = '%s'", s));
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set_randstate("000bad"); // Bad
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endfunction
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endclass
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module t(/*AUTOARG*/);
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initial begin
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Cls c;
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c = new;
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c.test;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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