// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0

`line
`line 100
`line 100 somefile 1
`line 100 "somefile"
`line 100 "somefile" 3
