forked from github/verilator
52912c6329
- Change .cvsignore to .gitignore - Remove Id metacomments - Cleanup whitespace at end of lines
42 lines
819 B
Verilog
42 lines
819 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t (clk);
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input clk;
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reg [43:0] mi;
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reg [5:0] index;
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reg read;
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integer cyc; initial cyc=1;
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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if (cyc==1) begin
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mi = 44'h123;
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end
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if (cyc==2) begin
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index = 6'd43;
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end
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if (cyc==3) begin
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read = mi[index];
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if (read!==1'b0) $stop;
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end
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if (cyc==4) begin
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index = 6'd44;
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end
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if (cyc==5) begin
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read = mi[index];
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$display("-Illegal read value: %x",read);
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//if (read!==1'b1 && read!==1'bx) $stop;
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end
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if (cyc==10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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