forked from github/verilator
17 lines
392 B
Systemverilog
17 lines
392 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2012 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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typedef struct packed { bit m; } struct_t;
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struct_t s;
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initial begin
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s.nfmember = 0; // Member not found
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$finish;
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end
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endmodule
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