forked from github/verilator
58 lines
1.5 KiB
Systemverilog
58 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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// verilator lint_off LATCH
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// verilator lint_off UNOPT
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// verilator lint_off UNOPTFLAT
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reg [31:0] runner; initial runner = 5;
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reg [31:0] runnerm1;
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reg [59:0] runnerq;
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reg [89:0] runnerw;
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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if (cyc==1) begin
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`ifdef verilator
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if (runner != 0) $stop; // Initial settlement failed
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`endif
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end
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if (cyc==2) begin
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runner = 20;
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runnerq = 60'h0;
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runnerw = 90'h0;
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end
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if (cyc==3) begin
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if (runner != 0) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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// This forms a "loop" where we keep going through the always till runner=0
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// This isn't "regular" beh code, but ensures our change detection is working properly
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always @ (/*AS*/runner) begin
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runnerm1 = runner - 32'd1;
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end
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always @ (/*AS*/runnerm1) begin
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if (runner > 0) begin
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runner = runnerm1;
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runnerq = runnerq - 60'd1;
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runnerw = runnerw - 90'd1;
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$write ("[%0t] runner=%d\n", $time, runner);
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end
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end
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endmodule
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